Recently, alternative nonvolatile memory devices such as phase change random access memory (PCRAM) devices, magnetic random access memory (MRAM) devices and ferroelectric random access memory (FRAM) devices having cell structures similar to those of DRAM devices, have been proposed and are being developed. A memory cell of a PCRAM generally includes a phase change element comprised of a chalcogenide alloy such as germanium antimony tellurium (“Este” or “GST”), for example, and a structure such as a transistor or other device that applies current to the phase change element (“PCE”). In one embodiment, one source/drain of the transistor may be coupled to ground with the other source/drain coupled to the PCE and the transistor gate coupled to a gate voltage. Another portion of the PCE may be coupled to a bit line voltage. According to this embodiment, when the data stored within the PCE is to be accessed, a voltage is applied to turn on the transistor and the bit line voltage is applied to the phase change material such that a read current may flow through the PCE and the transistor. Based on the level of output current, the data stored within the PCE is accessed.
Using the aforementioned arrangement or other arrangements, the level of output current depends upon the phase and impedance of the phase change material. By changing the phase of a phase change material such as from amorphous to crystalline or vice versa, the impedance of the phase change material may dramatically change. The changing impedance of the phase change material enables the phase change material to store different data. For example, the low-impedance form of the phase change material may store a data value of “1” whereas the high impedance form of the phase change material may store a data value of “0.”
There is ever-increasing pressure to reduce the size of the reaction, or contact, area of PCRAM cells. This is due to both increasing pressure to reduce the overall size of the cell, as well as the fact that a smaller reaction area results in a faster memory cell. Additionally, the process currently used to fabricate PCRAM cells can induce voids in the GST layer due to poor sealing layer coverage resulting in outgassing of the GST at high temperatures. In particular, poor step coverage will induce voids in the GST layer and will worsen outgassing when high temperatures (e.g., greater than 250° C.) are applied at the back end of the fabrication process.
Based on the foregoing, what is needed are PCRAM structures and methods for fabricating same that have smaller reaction areas and that do not suffer the GST void-inducing outgassing problems prevalent in current fabrication methods.